Circuit arrangement for pushbutton-controlled electronic parallel delivery of telegraphic impulses

ABSTRACT

A circuit arrangement for the parallel transmission of keyselectable telegraph impulses in which, in response to the actuation of a key, at least one impulse having a duration greater than 2 microseconds is produced and supplied to a parallel storer having at least as many storage places as the possible number of impulses in the telegraph code field, in which control means, including an impulse shortening circuit, is operative to terminate and transfer the impulses to be stored into the storer after a period of less than 2 microseconds.

United States Patent inventors Camillo Bodenstein;

Herbert Strassner, Muenchen, Germany Appl. No. 795,669 Filed Jan. 31,1969 Patented Feb. 16, 1971 Assignee Siemens Aktiengesellschalt Berlin,Germany Priority Feb. 2, 1968 Switzerland 1,639/68 CIRCUIT ARRANGEMENTFOR PUSHBUTTON- CONTROLLED ELECTRONIC PARALLEL DELIVERY OF TELEGRAPI-IICIMPULSES 5 Claims, 6 Drawing Figs.

US. Cl 178/ 17.5, 178/17; 340/345 Int. Cl H041 13/08, H041 15/04 Fieldof Search 178/1 7.5,

[56] References Cited UNITED STATES PATENTS 3,448,213 6/1969 Graf[78/175 3,456,077 7/1969 Jones, Jr 178/17 Primary Examiner- Kathleen H.Claffy Assistant ExaminerCharles W. Jirauch Attorney-Hill, Sherman,Meroni, Gross and Simpson ABSTRACT: A circuit arrangement for theparallel transmission of key-selectable telegraph impulses in which, inresponse to the actuation of a key, at least one impulse having aduration greater than 2 microseconds is produced and supplied to.

a parallel storer having at least as many storage places as the possiblenumber of impulses in the telegraph code field, in which control means,including an impulse shortening circuit, is operative to terminate andtransfer the impulses to be stored into the storer after a period ofless than 2 microseconds.

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- mum/70M Cam/l/o Horde/Islam Herbal! S/rassnor CIRCUIT ARRANGEMENT FORPUSI-IBUTTON- CONTROLLED ELECTRONIC PARALLEL DELIVERY OF TELEGRAPI-IICIMPULSES BACKGROUND OF THE INVENTION This invention is directed to anelectronic circuit arrangement for the transmission of impulses, such astelegraph impulses, which are selectable by means of actuating keys orthe like, whereby upon actuation of a respective key switch, means areoperative to cause the production of one or more impulses having alength of 2 to 3 microseconds, which are to be transferred to an n-placeparallel storer. Such impulses preferably are generated by connectingeach switch, operated by a respective key in a coder field, over an RCmember and cooperable diodes, the number of which corresponds to thenumber of n-code elements required for the particular teleprinter symbolinvolved. The condenser of such RC member is so dimensioned that underan impacting closure of the key switch the condenser is so charged bythe first closing of the contact that an impulse of a duration of 2 to 3microseconds is produced.

Problems arise in the operation of general circuits of the type inconnection with the possible formation of so-called mixed symbols, i.e.,erroneous impulse combinations caused bythe operation of two operatingkeys in rapid succession, and the invention is particularly directed toa circuit arrangement in which thepossibility of such double keyoperation is substantially eliminated.

SUMMARY OF THE INVENTION .deliberate very rapid consecutive operation oftwo keys is possible without the introduction of any errors in thetransmission.

In accordance with one embodiment of the invention these results areaccomplished in connection with a collector gate, to which the impulseor impulses appearing in the code field are directed, with the output ofsuch gate being supplied to a flip stage which functions as a transferblocking device. The

output condition present at such flip state is delayed for a period ofless than I or 2 microseconds and then conducted to input gates of thestorer, thereby terminating transfer of impulses from the code field tothe storer. Preferably. such delay periods amounts to approximately Imicrosecond.

In accordance with another embodiment of the invention,

the impulse or impulses appearing in the code field are directed to acollector gate, whereby an impulse present at the output of the gate isshortened by means of an impulse shor- ,tening stage to a duration ofless than I to 2 microseconds and the rear flank of such impulse isoperative to actuate a flip stage which is operative to block furthertransfer of impulses from the code field to the storer.

In accordance with a further embodiment of the invention, features ofboth of the previous embodiments are utilized to provide an arrangementparticularly suitable in the event contact impacts are to be expectedwithin the first few microseconds following key depression.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings wherein like referencecharacters indicate like or corresponding parts:

FIG. 1 represents a circuit diagram of a circuit arrangement inaccordance with the present invention employing static bistable flipstages;

FIG. 2 is an impulse diagram for the circuit illustrated in FIG. 1;

FIG. 3 is a circuit diagram similar to that of Figure I illustrating amodified arrangement employing dynamic flip stages; FIG. 4 is an impulsediagram for the circuit illustrated in FIG. 3;

' FIG. 5 is a circuit diagram, similar to FIGS. 1 and 3, illustrating afurther embodiment of this invention incorporating features of thecircuits of both F IGS., and

FIG. 6 is an impulse diagram for the circuit illustrated in FIG. 5.

DESCRIPTION OF'THE PREFERRED EMBODIMENTS This invention is particularlyapplicable to keyboard switching mechanisms such as those employed inelectronic teletypewriters and similar equipment in which the respectivekeys are arranged in a key field Tf in which respective key actuatedcontacts 1, assigned to the individual symbols or the like, are closedby the operation ofthe respective keys associated therewith. Based onpractical experience, such contacts are always considered as impactcontacts, but it is assumed that no impacts occur during the first 2microseconds. Line a of FIG. 2 thus may be considered as beingrepresentative of an impulse. sequence appearing immediately followingthe contacts 1 when actuated by the associated key, only three of thepossible 32 key controlled. current paths being illustrated. In order togenerate a clear brief impulse, an RC member follows each of thecontacts 1. With the exception of the impulse combination 5 X0, each ofthe RC membersis connected over diodes 2 and respective lines to thecoder field containing five main lines L1 to L5. Line 11 of FIG. 2 isillustrative of the impulses appearing at the input of a collector gate3 to which the lines L1 to L5 are connected. As illustrated in line c ofFIG. 2, the collection impulse appearing at the output of the gate 3 hasa fonn substantially as illustrated and a duration of approximately 3microseconds.

Each coder line L1L5 is also connected to respective storage flip stagesS1-S5 over corresponding gates Gl-GS which are preceded byrespectiveinverters J l-'J5. The outputs of the gates,GlG5 are alsoconnected to the flip stages SIS5 through respective gates G6-Gl0. Theoutput from the collector gate'3 is conducted over an impulse shorteningstage 7 and such output of the gate 3 is also connected over a gate 4 toa flip stageS, the output of which is conducted over an impulse delaystage 6 to the other inputs of the respective gates 01-65.

The operation of the circuit of FIG. 1 will be readily'apparent inconjunction with the impulse forms illustrated in FIG. 2. Consequently,upon closure of one of the keys and contacts 1 associated therewith,impulses will appear on the lines in accordance with the desired code tobe set by such key, which impulses will result in an impulse at theoutput of the collector gate 3 which will be conducted over the impulseshortening stage 7 to the gates G6Gl0 and over the gate'4 to the flipstage 85. As a result, the respective flip stages 81-85 will be set inaccordance with the desired-code, either over merely the inverters J1-J5and gates GIG5 or also over gates 06-010. The output of the flip stage 5(see line e of FIG. 2) after passing through the impulse delay stage 6,which delays the impulse by time T2 =l microsecond (see line f of FIG.2), blocks gates Gl-GS and prevents further impulse transfer over suchgates and at the same time blocks the gate 4 resulting in a shorteningof the setting impulse (see line d in FIG. 2) for the flip stage 5 whichforms the transfer block.

The release of such blocking action is effected by an impulselikeresetting of the flip stage 5 over the reset line h into its originalposition and may take place only after the collection impulse has beenterminated at c, i.e., after a duration of 3 microseconds, as otherwisethe storer would be reset again by the symbol still present at the linesLl-LS. Following the resetting of the flip stage, a new symbol can beimmediately placed on lines L1--L5 with a minimum time involvedcomprising 4 microseconds, which represent the cumulative time of thecollection impulse duration plus the reset impulse duration.

It is not necessary to erase the stages S1 to S of the parallel registerbetween symbols as the register may be merely reset or rather overset byeach new symbol. As a result, the impulse shortening time T1 of theimpulse shortening stage 7, as illustrated in FIG. 2 for the impulse g(see line g of FIG. 2), must be smaller than T2.

The impulses appearing at the five outlets of the storers are conductedto a parallel-series symbol converter or an appropriate, preferablyelectronic receiver.

The circuit disclosed is very efficient, assuring with a very highdegree of probability the prevention of the recording of mixed symbols,and at the same time, as demonstrated by experiments, makes possibleextremely rapid sequences of key operation.

Instead of the so-called RS flip-flops (static bistable flip stages)employed in the embodiment of FIG 1, dynamic flip stages such as delayflip-flops may be utilized as illustrated in FIG. 3 with FIG. 4illustrating the impulse forms associated with this circuit.

This construction employs the same circuitry for generation of theactuating impulses as illustrated in lines a and b of FIG. 4, and thelines LlL5 are connected to a collection gate 13, generallycorresponding to the gate 3, but produces a negated impulse k (see linek of FIG. 4) as compared with the impulses c of the circuit of FIG. 1.The impulses b in this case are transmitted to preparation inputs ofstorage flip stages S21-S25 as well as to the collector gate 13. Thus,upon actuation of any key a negative collection impulse k of about 3microseconds duration will appear at the output of the collector gate13. Such collection impulse is conducted to an impulse shortening stage14 which results in a shortening of the impulse to a time of less than 1microsecond. As the preparation input of such flip stage is permanentlyconnected to high potential, the positive flank of the shortenedimpulses appearing at m sets a flip stage 15 (see line m of Fig. 4). Theoutput of the flip stage 15 is conducted to the flip stages 521-825 ofthe parallel register whereby the positive timing flank of the impulsewill trigger the flip stages of the register to complete impulsetransfer therein. Thus, both adequate setup time (=T2) and hold time(=collector impulse T2) are available.

It will be apparent that a renewed setting of the flip stage 15 and thusof the register by a renewed striking of the key is impossible as longas the flip stage 15 has not been reset by means of its static input atp. However, in contrast to the circuit illustrated in FIGS. 1 and 2, theresetting of the timing stage 15 can take place immediately after thesetting as any collection impulse still present at a can produce nopositive timing flank at m. Consequently, a second symbol can be typedand identified by the flip stage only after completion of the firstcollection impulse at k so that a new negative flank can occur at thispoint. The time between the depression of two keys thus may have aminimum of 3 microseconds, providing that the receiver connected at thekeyboard outlet, for example, a parallel-series converter indicated asPSU, is able to process the first symbol within such time.

If contact impacts are to be expected within the first few microsecondsa circuit comprising a combination of those of FIGS. 1 and 3 may beutilized, such as illustrated in FIG. 5, in which the parallel register$31-$35 receives the spacing impulses over the timing inputs while themarking impulses are fed over the static flip stage inputs. In such casethe preparation inputs would permanently lie on high potential. However,in this arrangement the flip stages employed should be those in whichthe static inputs dominate the dynamic inputs, i.e., if concurrentlyover this dynamic input one condition is to be produced and over thestatic input the opposite condition is to be produced, the flip stageinvolved will certainty assume the condition required by the staticinput. Inverters 1115 and gates GIL-G15 correspond to the like invertersof FIG. 1 and gates $31-$35 correspond to the gates 01-05 of FIG. I. Aswill be apparent from the impulse diagram of FIG. 6, the generaloperation is quite similar to that of the circuit of FIG. 1, with theexception of differences in the actuation and operation of the flipstages, the respective pulse of the lettered lines appearing at thiscorrespondingly identified points of FIG. 5. Thus, a synchronizingimpulse occurs at q with every key stroke, independently of the coding,which is applied to the respective flip stages S3l-S35.

It will be apparent that mixed symbol formation can occur in thesecircuits only when two keys are depressed within the time of theshortened collection impulse. Thus, for example, if such time is madeT2=1 microsecond, at an average stroke speed of 50 cm/second, in orderto obtain a mixed symbol two keys would have to be operated within avertical difference of 0.5 u m. This value is far below the mechanicaltolerances in key structures and indicates the improbability of eventhis rare case occurring in practical operations. Experiments haveconfirmed this fact.

Having thus defined our invention, it will be apparent to those skilledin the art from the disclosure herein given that various immaterialmodifications may be made in the same without departing from the spiritof our. invention.

We claim:

1. In a circuit arrangement for the parallel transmission ofkey-selectable telegraphic code impulses in which, in response to theactuation of a key, at least one impulse having a duration greater than2 us is produced and supplied to a parallel storer having at least asmany storage places as the possible number of impulses in the telegraphfield, the combination of means connected to the storer for feeding acontrol signal thereto for controlling the termination 2 #8. storageoperations thereof, and means disposed to receive such control impulsesfor producing an impulse following a duration less than that of saidcontrol impulse such produced impulse being conducted to said storer andoperative to effect termination of the storage operation after a storageperiod of less than 2 ts.

2. A circuit arrangement according to claim 1 comprising in furthercombination gates disposed at the respective signal inputs of saidstorer, a collector gate to which the code impulses are conducted, aflip stage to which an impulse appearing at the output of said collectorgate is conducted, and impulse delay means connecting the output of saidflip stage to said storer input gates, operative to delay a blockingimpulse thereto for a period up to 2 as.

3. A circuit arrangement as defined in claim 2, wherein the markingimpulses corresponding to the code combinations are fed over staticinputs of the parallel storage flip stages and the spacing impulses overthe dynamic preparatory inputs of said flip stages, with the preparatoryinputs lying continuously at a high potential, said flip stages havingstatic inputs which dominate the dynamic inputs.

4. A circuit arrangement according to claim 1, comprising in furthercombination, a collector gate to which the code impulses are conducted,a flip stage, impulse shortening means operatively connecting the outputof said collector gate to said flip stage, the output of said flip stagebeing connected to the storer for initiating the storage operation, saidimpulse shortening means shortening the received impulse to less. than 2,us, with the rear flank thereof being operative to actuate said flipstage.

5. A circuit arrangement as defined in claim 4, wherein the markingimpulses corresponding to the code combinations are fed over staticinputs of the parallel storage flip stages and the spacing impulses overthe dynamic preparatory inputs of said flip stages, with the preparatoryinputs lying continuously at a high potential, said flip stages havingstatic inputs which dominate the dynamic inputs.

1. In a circuit arrangement for the parallel transmission ofkey-selectable telegraphic code impulses in which, in response to theactuation of a key, at least one impulse having a duration greater than2 Mu s is produced and supplied to a parallel storer having at least asmany storage places as the possible number of impulses in the telegraphfield, the combination of means connected to the storer for feeding acontrol signal thereto for controlling the termination 2 Mu s. storageoperations thereof, and means disposed to receive such control impulsesfor producing an impulse following a duration less than that of saidcontrol impulse such produced impulse being conducted to said storer andoperative to effect termination of the storage operation after a storageperiod of less than 2 Mu s.
 2. A circuit arrangement according to claim1 comprising in further combination gates disposed at the respectivesignal inputs of said storer, a collector gate to which the codeimpulses are conducted, a flip stage to which an impulse appearing atthe output of said collector gate is conducted, aNd impulse delay meansconnecting the output of said flip stage to said storer input gates,operative to delay a blocking impulse thereto for a period up to 2 Mu s.3. A circuit arrangement as defined in claim 2, wherein the markingimpulses corresponding to the code combinations are fed over staticinputs of the parallel storage flip stages and the spacing impulses overthe dynamic preparatory inputs of said flip stages, with the preparatoryinputs lying continuously at a high potential, said flip stages havingstatic inputs which dominate the dynamic inputs.
 4. A circuitarrangement according to claim 1, comprising in further combination, acollector gate to which the code impulses are conducted, a flip stage,impulse shortening means operatively connecting the output of saidcollector gate to said flip stage, the output of said flip stage beingconnected to the storer for initiating the storage operation, saidimpulse shortening means shortening the received impulse to less than 2Mu s, with the rear flank thereof being operative to actuate said flipstage.
 5. A circuit arrangement as defined in claim 4, wherein themarking impulses corresponding to the code combinations are fed overstatic inputs of the parallel storage flip stages and the spacingimpulses over the dynamic preparatory inputs of said flip stages, withthe preparatory inputs lying continuously at a high potential, said flipstages having static inputs which dominate the dynamic inputs.